10 GHz, 20mW, fast locking, adaptive gain PLLs with on-chip frequency calibration for agile frequency synthesis in a .18μm digital CMOS process

被引：12

作者：

Ravi, A ^{[1
]}

Banerjee, G ^{[1
]}

Bishop, RE ^{[1
]}

Bloechel, BA ^{[1
]}

Carley, LR ^{[1
]}

Soumyanath, K ^{[1
]}

机构：

[1] Intel Corp, Intel Labs, Commun & Interconnect Technol, Hillsboro, OR 97124 USA

来源：

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VLSIC.2003.1221197

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

This paper describes two fully integrated 10GHz PLLs with an LCVCO implemented in a 0.18um native digital CMOS process. In the first version, an adaptive gain circuit along with a wide-swing charge pump improves the lock range and ensures faster settling. The PLL has a 1.6GHz tuning range, a 0.5mus settling time (for a frequency step equal to 10% of the tuning range), reference sideband power of 58dBc and phase noise of -105dBc/Hz at a 10kHz offset and 120dBc/Hz at a 20MHz offset (rms jitter of 1.3ps) while dissipating less than 20mW from a 1.6V power supply. Enhancing the process with deep n-wells appears to improve the noise isolation of the circuit by about 5dB. The second variant incorporates a combination of coarse and fine tuning for the VCO along with a new frequency calibration circuit based on a digital quadri-correlator. This PLL has a 1.25GHz tuning range, a 10mus settling time, a reference sideband power below the noise floor and a phase noise of -105dBc/Hz at 10kHz and -130dBc/Hz at 20MHz from the carrier (rms jitter of 1.2ps).

引用

页码：181 / 184

页数：4