Razor: Circuit-level correction of timing errors for low-power operation

被引：256

作者：

Ernst, D ^{[1
]}

Das, S ^{[1
]}

Lee, S ^{[1
]}

Blaauw, D ^{[1
]}

Austin, T ^{[1
]}

Mudge, T ^{[1
]}

Kim, NS ^{[1
]}

Flautner, K ^{[1
]}

机构：

[1] Univ Michigan, Adv Comp Architecture Lab, Ann Arbor, MI 48109 USA

来源：

IEEE MICRO | 2004年 / 24卷 / 06期

关键词：

D O I：

10.1109/MM.2004.85

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

DYNAMIC VOLTAGE SCALING IS ONE OF THE MORE EFFECTIVE AND WIDELY USED METHODS FOR POWER-AWARE COMPUTING. HERE IS A DVS APPROACH THAT USES DYNAMIC DETECTION AND CORRECTION OF CIRCUIT TIMING ERRORS TO TUNE PROCESSOR SUPPLY VOLTAGE AND ELIMINATE THE NEED FOR VOLTAGE MARGINS.

引用

页码：10 / 20

页数：11

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