Worst-case bias during total dose irradiation of SOI transistors

被引:118
作者
Ferlet-Cavrois, V
Colladant, T
Paillet, P
Leray, JL
Musseau, O
Schwank, JR
Shaneyfelt, MR
Pelloie, JL
de Poncharra, JD
机构
[1] CEA, DIF, F-91680 Bruyeres Le Chatel, France
[2] Sandia Natl Labs, Albuquerque, NM 87185 USA
[3] LETI, CEA, DTA, F-38054 Grenoble, France
关键词
D O I
10.1109/23.903751
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
The worst case bias during total dose irradiation of partially depleted SOI transistors from two technologies is correlated to the device architecture. Experiments and simulations are used to analyze SOI back transistor threshold voltage shift and charge trapping in the buried oxide.
引用
收藏
页码:2183 / 2188
页数:6
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