A Hardware Architecture for the Affine-Invariant Extension of SIFT

被引：4

作者：

Yum, Joohyuk ^{[1
]}

Lee, Chul-Hee ^{[2
]}

Park, Jinwoo ^{[2
]}

Kim, Jin-Sung ^{[3
]}

Lee, Hyuk-Jae ^{[2
]}

机构：

[1] Samsung Elect Corp, Syst LSI Div, Hwaseong 18448, South Korea

[2] Seoul Natl Univ, Dept Elect & Comp Engn, Interuniv Semicond Res Ctr, Seoul 151744, South Korea

[3] Sun Moon Univ, Dept Elect Engn, Asan 31460, South Korea

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS FOR VIDEO TECHNOLOGY | 2018年 / 28卷 / 11期

关键词：

Hardware accelerator; scale-invariant feature transform (SIFT); affine-invariant extension of SIFT (ASIFT); affine transform hardware;

D O I：

10.1109/TCSVT.2017.2740175

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

Affine-invariant extension of scale-invariant feature transform (ASIFT) algorithm requires a large amount of computation and memory access, and consequently, is hard to process in real time. In order to increase the operation speed of ASIFT algorithm, this paper proposes a new hardware architecture for the ASIFT algorithm. In order to reduce the memory access time, the affine transform is modified to allow external memory access in the raster-scan order with a little accuracy drop. In addition, image filtering with skewed kernel is proposed in order to reduce the memory space for image storage. Additional complexity reduction is attempted to reduce the number of simulated viewpoints. As a result, throughput of the affine transform module is increased to 325% and the proposed hardware processes a video graphics array-sized (640 x 480) video at 20 fps.

引用

页码：3251 / 3261

页数：11

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