Design and analysis of a high-speed comparator in a pipelined ADC

被引：0
|
作者：
Yang, Wen-Rong [1 ]
Wang, Jia-Dong [1 ]
机构：
[1] Shanghai Univ, Key Lab Adv Display & Syst Applicat, Minist Educ, Microelect Res & Dev Ctr, Shanghai 200072, Peoples R China
来源：
HDP'07: PROCEEDINGS OF THE 2007 INTERNATIONAL SYMPOSIUM ON HIGH DENSITY PACKAGING AND MICROSYSTEM INTEGRATION | 2007年
关键词：
high speed; pipelined; ADC; analog-to-digital converters; comparator;
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper presents a kind of high-speed voltage difference comparator. The comparator consists of pre-amplifier stage and dynamic latch with reset port. Based on standard 0.35 um/5 v CMOS process model, the circuit is simulated with Cadence EDA software. By analysis of circuit and EDA simulation, the comparator has the characteristics with high speed, good precision and low power dissipation. And it is suitable for the A/D converter with pipeline structure.
引用
收藏
页码：340 / +
页数：2
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