Increase Power Density and Simplify Designs with 3D SiP Modules

被引：0

作者：

Moss, Jim ^{[1
]}

Chaudhry, Usman ^{[2
]}

Kummerl, Steven

DeVries, Charles ^{[2
]}

机构：

[1] Silicon Valley Analog, Texas Instruments, Silicon Valley, CA USA

[2] Texas Instruments Inc, Isolat & Syst Package Modules Grp Semicond Packag, Hyderabad, Telangana, India

来源：

2016 INTERNATIONAL SYMPOSIUM ON 3D POWER ELECTRONICS INTEGRATION AND MANUFACTURING (3D-PEIM) | 2016年

关键词：

Power Integrated Circuits; Electronics Packaging; Multichip modules; DC-DC power converters;

D O I：

暂无

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This paper will discuss volumetric co-design methodology and packaging construction trade-offs for 3D SiP power modules. It will provide more details on SiP eco-system, co-design, construction, materials and circuit topology. Today, designers are demanding an overall form-factor reduction to save board space, increase functionality, and allocate more real estate toward end-user applications - all with less space allocated to power management where not just the X-Y shrink but the 3D volumetric shrink is required. For example, in wearable products, the semiconductor industry has recently seen an increase in the use of system-in-package (SiP) technology for users who want simpler, more flexible designs and need to fulfill challenging space requirements. And we expect to see this trend continue.

引用

页数：2