Design methodology for on-chip interconnects

被引：0

作者：

Cases, M ^{[1
]}

Smith, H ^{[1
]}

Bowen, M ^{[1
]}

机构：

[1] IBM Corp, Austin, TX 78758 USA

来源：

ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING | 1998年

关键词：

D O I：

10.1109/EPEP.1998.733493

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A design methodology for on-chip interconnects which utilizes fast circuit simulator techniques to control signal coupling and transition rate degradation is described. CMOS process technology trends and their effects on interconnect performance are discussed. Critical design parameter curves are used to optimize a set of wire geometries that satisfies the electrical constraints for high density chips.

引用

页码：27 / 30

页数：4

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