A new scaling theory for fully-depleted SOI double-gate MOSFET's: including effective conducting path effect (ECPE)

被引：20

作者：

Chiang, TK ^{[1
]}

机构：

[1] So Taiwan Univ Technol, Dept Elect Engn, Tainan 710, Taiwan

来源：

SOLID-STATE ELECTRONICS | 2005年 / 49卷 / 03期

关键词：

D O I：

10.1016/j.sse.2004.10.008

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A new scaling theory for fully-depleted double-gate (DG) SOI MOSFET's is established, which gives a guidance for the device design so that maintaining a precise subthreshold factor for given device parameters. By investigating the subthreshold conducting phenomenon of DG MOSFET's, the effective conducting path effect (ECPE) is employed to obtain the natural length lambda(3) to guide the design. With ECPE, the minimum channel potential phi d(eff,min) shows the new scaling factor alpha(3) to model the subthreshold behavior. Compared to conventional scaling rule, our model accounting for ECPE caused by substrate doping density not only provides a unified scaling rule but also offers the basic designing guidance for fully-depleted DG SOI MOSFET's. (C) 2004 Elsevier Ltd. All rights reserved.

引用

页码：317 / 322

页数：6

共 13 条

[1] GENERALIZED GUIDE FOR MOSFET MINIATURIZATION [J].

BREWS, JR ;

FICHTNER, W ;

NICOLLIAN, EH ;

SZE, SM .

ELECTRON DEVICE LETTERS, 1980, 1 (01) :2-4

[2] A comprehensive analytical subthreshold swing (S) model for double-gate MOSFETs [J].

Chen, Q ;

Agrawal, B ;

Meindl, JD .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 2002, 49 (06) :1086-1090

[3]

CHIANG TK, 2004, J SEMICOND SCI TECHN

[4]

ENDOH T, 1999, IEICE, V82, P72

[5] Device scaling limits of Si MOSFETs and their application dependencies [J].

Frank, DJ ;

Dennard, RH ;

Nowak, E ;

Solomon, PM ;

Taur, Y ;

Wong, HSP .

PROCEEDINGS OF THE IEEE, 2001, 89 (03) :259-288

[6]

*MEDICI, 1998, 2 DIM DEV SIM PROGR

[7] SCALING THEORY FOR DOUBLE-GATE SOI MOSFETS [J].

SUZUKI, K ;

TANAKA, T ;

TOSAKA, Y ;

HORIE, H ;

ARIMOTO, Y .

IEEE TRANSACTIONS ON ELECTRON DEVICES, 1993, 40 (12) :2326-2329

[8]

TAUR T, 1999, P INT S VLSI TECHN S, P6

[9] CMOS scaling into the nanometer regime [J].

Taur, Y ;

Buchanan, DA ;

Chen, W ;

Frank, DJ ;

Ismail, KE ;

Lo, SH ;

SaiHalasz, GA ;

Viswanathan, RG ;

Wann, HJC ;

Wind, SJ ;

Wong, HS .

PROCEEDINGS OF THE IEEE, 1997, 85 (04) :486-504

[10] 25 nm CMOS design considerations [J].

Taur, Y ;

Wann, CH ;

Frank, DJ .

INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :789-792

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