Large-Scale Power Combining and Mixed-Signal Linearizing Architectures for Watt-Class mmWave CMOS Power Amplifiers

被引:37
作者
Bhat, Ritesh [1 ]
Chakrabarti, Anandaroop [1 ]
Krishnaswamy, Harish [1 ]
机构
[1] Columbia Univ, Dept Elect Engn, New York, NY 10027 USA
关键词
45; GHz; device stacking; digital-mmWave data conversion; linearization techniques; millimeter-wave integrated circuits; power amplifier; power combiner; SOI CMOS proces; HIGH-EFFICIENCY; SOI;
D O I
10.1109/TMTT.2014.2387055
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Millimeter wave (mmWave) CMOS power amplifiers (PAs) have traditionally been limited in output power due to the low breakdown voltage of scaled CMOS technologies and poor quality of on-chip passives. Moreover, high data-rates and efficient spectrum utilization demand highly linear PAs with high efficiency under back-off. A novel linearizing architecture which simultaneously employs large-scale power combining, linearization through dynamic load modulation, and improved efficiency under back-off by supply-switching and load modulation is introduced. A quarter-wave combiner that exploits lumped spiral inductor equivalents of quarter-wave transmission lines with higher characteristic impedance enables one-step, low-loss, eight-way combining with a measured efficiency of 75% at 45 GHz. Eight-way combining of stacked SOI CMOS PAs results in a PA array with watt-class (>27 dBm) saturated output power (3x higher than prior art) and ultra-wideband operation (33-46 GHz) in 45 nm SOI CMOS. Another 45 nm SOI CMOS prototype, a three-bit digital to mmWave PA array, utilizing the proposed linearizing architecture achieves 23.3 dBm of saturated output power at 42.5 GHz, PAE(-6dB)/PAE(peak) = 67.7% as well as excellent linearity (DNL < 0.5 LSB} and INL < 1 LSB using end-point fit).
引用
收藏
页码:703 / 718
页数:16
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