A parallel ASIC architecture for efficient fractal image coding

Fractal image coding is a compression technique with many promising features, but it has been primarily placed in the class of archival coding algorithms due to its computationally expensive encoding algorithm. Though fractal coding has been extensively optimized for speed, it is still not practical for real-time applications on most sequential machines. The problem with fractal coding lies in the large amount of pixel block comparisons that are required, which makes fractal coding better suited toward parallel systems. At the same time, VLSI area has become a much less important constraint in chip design due to better fabrication techniques and smaller micron technologies. This has lead to a recent trend for designing parallel subsystems and including multimedia ASIC circuitry on general purpose CPUs. In this paper, we will present a parallel ASIC array architecture for use in fractal encoding that performs a full domain quad-tree search in near real-time for standard sized gray scale images. The design is also scalable so that larger images can be encoded faster by adding chips to the array. In designing this architecture, we include novel optimizations at the algorithmic, architecture, and circuit levels.