Speed binning with path delay test in 150-nm technology

被引：72
作者：
Cory, BD
Kapur, R
Underwood, B
机构：
[1] nVidia, San Jose, CA USA
[2] Synopsys, Mountain View, CA 94043 USA
来源：
IEEE DESIGN & TEST OF COMPUTERS | 2003年 / 20卷 / 05期
关键词：
SELECTION;
D O I：
10.1109/MDT.2003.1232255
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
What would it take to reduce speed binning's dependency on functional testing? One answer is a structural at-speed test approach that can achieve the same effectiveness as functional testing. The authors of this article offer a formula to relate structural critical-path testing frequency to system-operation frequency. They demonstrate that there can be a high correlation between frequencies resulting from structural testing and those resulting from functional testing.
引用
收藏
页码：41 / 45
页数：5
相关论文
共 12 条
[1]  
[Anonymous], P IEEE INT TEST C SE
[2]   ON PATH SELECTION IN COMBINATIONAL LOGIC-CIRCUITS [J].
LI, WN ;
REDDY, SM ;
SAHNI, SK .
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1989, 8 (01) :56-63
[3]  
LIOU JJ, 2000, P IEEE VLSI TEST S A, P97
[4]   Comparing functional and structural tests [J].
Maxwell, P ;
Hartanto, I ;
Bentz, L .
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :400-407
[5]  
Nigh P, 2000, INT TEST CONF P, P454
[6]  
Park E. S., 1991, Proceedings. International Test Conference 1991 (IEEE Cat. No.91CH3032-0), P897, DOI 10.1109/TEST.1991.519756
[7]   Too much delay fault coverage is a bad thing [J].
Rearick, J .
INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :624-633
[8]   Testing of critical paths for delay faults [J].
Sharma, M ;
Patel, JH .
INTERNATIONAL TEST CONFERENCE 2001, PROCEEDINGS, 2001, :634-641
[9]   Enhanced delay defect coverage with path-segments [J].
Sharma, M ;
Patel, JH .
INTERNATIONAL TEST CONFERENCE 2000, PROCEEDINGS, 2000, :385-392
[10]   Binning for IC quality: Experimental studies on the SEMATECH data [J].
Singh, AD ;
Lakin, DR ;
Sinha, G ;
Nigh, P .
1998 IEEE INTERNATIONAL SYMPOSIUM ON DEFECT AND FAULT TOLERANCE IN VLSI SYSTEMS, PROCEEDINGS, 1998, :4-10
12