Improving the performance of incremental encoders with conditioning circuits based on FPGA

被引：5

作者：

Quintans, Camilo ^{[1
]}

Farina, Jose ^{[1
]}

Marcos-Acevedo, Jorge ^{[1
]}

机构：

[1] Univ Vigo, Dept Elect Technol, Vigo 36310, Spain

来源：

MEASUREMENT | 2016年 / 90卷

关键词：

Field programmable gate arrays; Incremental encoder; Position measurement;

D O I：

10.1016/j.measurement.2016.04.031

中图分类号：

T [工业技术];

学科分类号：

08 ;

摘要：

This work presents a conditioning circuit to improve the performance of incremental encoders that allows multiplying the number of counts by four with a high speed response. This circuit is described in VHDL and is synthesized for an FPGA so it can be included in an embedded system. Practical results of the solution, both from simulation and actual data, are presented. (C) 2016 Elsevier Ltd. All rights reserved.

引用

页码：1 / 3

页数：3