A New Quasi-3-D Compact Threshold Voltage Model for Pi-Gate (ΠG) MOSFETs With the Interface Trapped Charges

被引：4

作者：

Chiang, Te-Kuang ^{[1
]}

机构：

[1] Natl Univ Kaohsiung, Adv Devices Simulat Lab, Dept Elect Engn, Kaohsiung 800, Taiwan

来源：

IEEE TRANSACTIONS ON NANOTECHNOLOGY | 2015年 / 14卷 / 03期

关键词：

Equivalent number of gates (ENG); normalized gate extension depth (NGED); pi-gate (Pi G) MOSFETs; quasi-3-D scaling equation; short-channel effects (SCEs); virtual back gate (VBG) effects; UNIVERSAL CORE MODEL; DRAIN-CURRENT MODEL; SCALING THEORY; SIMULATION;

D O I：

10.1109/TNANO.2015.2416198

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

With the effects of equivalent oxide charges on the flat-band voltage, a new quasi-three-dimensional (quasi-3-D) compact threshold voltage model is presented for the pi-gate (Pi G) MOSFETs with the interface trapped charges based on the quasi-3-D scaling equation that accounts for equivalent number of gates and virtual back gate effects induced by the normalized gate extension depth in the buried oxide. The model reveals that a thin gate oxide can effectively reduce the threshold voltage degradation caused by the trapped charges. Opposite to the thin gate oxide, a thick silicon is required to alleviate the threshold voltage shift resulted from the negative trapped charges. For the short-channel behavior, the device with negative/positive trapped charges can decrease/increase the threshold voltage roll-off caused by the short-channel effects. Due to its computational efficiency and simple formula, the model can be easily used to explore the threshold behavior for the charges trapping Pi G MOSFETs.

引用

页码：555 / 560

页数：6

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