A simple, digital method for background estimation of timing mismatches in time-interleaved ADCs

被引：1
|
作者：
Konopacki, Jacek [1 ]
Machniewski, Jan [1 ]
机构：
[1] Politech Slaska, Katedra Elekt Elektrotech & Mikroelekt, Ul Akad 16, PL-44100 Gliwice, Poland
来源：
PRZEGLAD ELEKTROTECHNICZNY | 2022年 / 98卷 / 09期
关键词：
time interleaved ADC; timing mismatch; digital calibration; background estimation; SKEW ESTIMATION; CALIBRATION;
D O I：
10.15199/48.2022.09.39
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
The article presents a modification of two-stage difference-based estimation method of timing mismatches in time-interleaved ADCs. The presented solution eliminates the limitations of the original method and requires a smaller number of arithmetic operations. The proposed approach was verified with simulations by carrying out various tests.
引用
收藏
页码：174 / 177
页数：4
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