Software Architecture of High Efficiency Video Coding for Many-Core Systems with Power-Efficient Workload Balancing

被引：0

作者：

Khan, Muhammad Usman Karim ^{[1
]}

Shafique, Muhammad ^{[1
]}

Henkel, Joerg ^{[1
]}

机构：

[1] Karlsruhe Inst Technol, CES, D-76021 Karlsruhe, Germany

来源：

2014 DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION (DATE) | 2014年

关键词：

COMPLEXITY REDUCTION SCHEME;

D O I：

暂无

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

The High Efficiency Video Coding (HEVC) standard aims at providing similar to 50% better compression compared to its predecessor (H.264) at the cost of high computational complexity. To enable HEVC video encoding in real-time scenarios, special coding support for parallelization is provided in HEVC that can be exploited by many-core systems. In this work, we present a HEVC software architecture where a video frame is adaptively divided into independent video frame regions (i.e. so-called video tiles) which are processed concurrently on multiple cores. By balancing the workload of each video tile mapped to a particular core, the total power consumption of a system is reduced (through dynamically scaling the operating frequency) under a given frame-rate constraint. We also exploit user tolerance to further curtail the HEVC workload with insignificant video quality degradation. Experimental results illustrate that the proposed approach results in similar to 43% power savings on a many-core system.

引用

页数：6