A floating-gate-MOS-based low-power CDMA matched filter employing capacitance disconnection technique

被引：10

作者：

Yamasaki, T ^{[1
]}

Fukuda, T ^{[1
]}

Shebata, T ^{[1
]}

机构：

[1] Univ Tokyo, Dept Elect Engn, Bunkyo Ku, Tokyo 1138656, Japan

来源：

2003 SYMPOSIUM ON VLSI CIRCUITS, DIGEST OF TECHNICAL PAPERS | 2003年

关键词：

D O I：

10.1109/VLSIC.2003.1221223

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

Low-power and compact CDMA matched filters have been developed based on the floating-gate MOS technology. The low-power operation has been achieved by employing the single-step matching scheme and disconnecting the coupling-capacitors unnecessary for the matching operation. The 255-chip matched filter fabricated in a 0.35-mum technology demonstrated 6mW operation at 3V power supply and the chip rate of 5MS/s, while occupying the chip area of 1.0 mm(2).

引用

页码：267 / 270

页数：4

共 33 条

[1] A low-power floating-Gate-MOS-based CDMA matched filter featuring coupling capacitor disconnection
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[2] A high-speed median filter VLSI using floating-gate-MOS-based low-power majority voting circuits
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