A High-Density and Low-Crosstalk Differential Pin Map for 112 Gb/s PAM4 Applications

The rapidly growing demand for high-bandwidth data rate has pushed the wireline communications speed up to 112 Gb/s. In such high-speed and high-channel-count applications, a major challenge for differential pin map design is the tradeoff between cost and the crosstalk between differential pairs in the area of BGA pins and PCB via connection. In this letter, a pin map pattern with a high signal-to-ground ratio (S:G) of 1:1.25 and low crosstalk is proposed. Compared with the conventional pin map pattern in a square array with S:G = 1:1, the integrated crosstalk noise (ICN) is reduced by 75% and the insertion loss to crosstalk ratio (ICR) is increased by 13 dB. Compared with the conventional pin map pattern in a triangular array with S:G = 1:1.5, the ICN is reduced by 20%, and the ICR is improved by 3 dB.