A 2.2Gbps CMOS look-ahead DFE receiver for multidrop channel with pin-to-pin time skew compensation

被引：22

作者：

Sohn, YS ^{[1
]}

Bae, SJ ^{[1
]}

Park, HJ ^{[1
]}

Kim, CH ^{[1
]}

Cho, SI ^{[1
]}

机构：

[1] Pohang Univ Sci & Technol, Dept EE, Pohang, South Korea

来源：

PROCEEDINGS OF THE IEEE 2003 CUSTOM INTEGRATED CIRCUITS CONFERENCE | 2003年

关键词：

D O I：

10.1109/CICC.2003.1249443

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A CMOS LADFE (look-ahead decision feedback equalization) receiver with a pin-to-pin time skew compensation was proposed and implemented for high-speed chip-to-chip communication such as multi-drop DRAM interface. The look-ahead scheme in DFE input buffer increased the maximum data rate from 1.4Gbps to 2.2Gbps. Different sampling clock was synthesized for each pin by using an X2 over-sampling scheme. Active chip area per pin is 100umx800um with a 2.5V, 0.25um CMOS process.

引用

页码：473 / 476

页数：4

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