High-performance VLSI architecture of multiplierless LMS adaptive filters using distributed arithmetic

Currently, considerable research is being performed on multiplierless structural methods for fixed coefficient filters, but not much research has been done on structural methods for creating adaptive filters whose coefficients vary with time. A few multiplierless structural methods have been proposed as structural methods using distributed arithmetic, but these conventional methods use particular encoding for input signals, and thus experience very high levels of degradation in their convergence characteristics. The authors improve significantly the convergence characteristics by generalizing this method using a new two's complement method. In addition, the authors propose a VLSI architecture not considered in conventional methods and perform VLSI evaluations of their structural method. The results show that the authors' proposed method can dramatically reduce power consumption and hardware requirements while sustaining high performance and very low latency compared to structural methods that use a multiplier. (C) 2001 Scripta Technica.