Strain-engineering in nanowire field-effect transistors at 3 nm technology node

Toward extreme scaling of CMOS transistors, it is being predicted by IRDS that some sort of gate-all-around FinFET structure (nanowire or nanosheet type of devices) will be essential in 5 nm technology node and below. Thus, it is time for exploring new device structures through simulations. In this work, as a proof-of-concept, a comparative study of bulk-Si channel, Si-channel with epi-SiGe source/drain stressor and uniaxially strained-SiGe channel nanowire field-effect transistors at 3 nm technology node has been performed using predictive TCAD simulations. Uniaxial compressive strain due to lattice mismatch is found to be more effective for boosting device performance of strained-SiGe channel nanowire FETs. Detailed analyses of performance comparison with conventional bulk-Si channel nanowire transistors are reported.