5-V Buck Converter Using 3.3-V Standard CMOS Process With Adaptive Power Transistor Driver Increasing Efficiency and Maximum Load Capacity

被引:42
作者
Nam, Hyunseok [1 ]
Ahn, Youngkook [1 ]
Roh, Jeongjin [1 ]
机构
[1] Hanyang Univ, Dept Elect Engn, Ansan 426791, South Korea
基金
新加坡国家研究基金会;
关键词
Adaptive power transistor driver; cascode power transistor; conduction loss; dc-dc converter; maximum allowable voltage; DESIGN; MANAGEMENT;
D O I
10.1109/TPEL.2010.2091287
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
A high-voltage-tolerant buck converter with a novel adaptive power transistor driver is proposed in this paper. In order to minimize the R-ON of the cascode power transistor, the proposed scheme uses optimized and separated driving voltages for bias of the pMOS and nMOS power transistors. This increases not only the conversion efficiency, but also the maximum allowable load current for the transistor driver with small layout size, when compared to the buck converter with the earlier scheme. The measurements show that when the supply voltage is 2.5 V and the load current is 150 mA, the efficiency of the buck converter with the earlier scheme is 82%, whereas the efficiency of the buck converter with the proposed scheme is 92%, showing a maximum improvement of 10%. The designed buck converter uses the 0.35-mu m-thick gate oxide CMOS process, and at 2.5-5 V of voltage, can supply up to 380 mA of load current. The total chip size is 2.7 mm(2).
引用
收藏
页码:463 / 471
页数:9
相关论文
共 21 条
[1]   A Fully Integrated 660 MHz Low-Swing Energy-Recycling DC-DC Converter [J].
Alimadadi, Mehdi ;
Sheikhaei, Samad ;
Lemieux, Guy ;
Mirabbasi, Shahriar ;
Dunford, William G. ;
Palmer, Patrick R. .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2009, 24 (5-6) :1475-1485
[2]   5.5-V I/O in a 2.5-V 0.25-μm CMOS technology [J].
Annema, AJ ;
Geelen, GJGM ;
de Jong, PC .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2001, 36 (03) :528-538
[3]  
Ballan H., 1999, High voltage devices and circuits in standard CMOS technologies
[4]  
Bult K., 1999, 1999 IEEE International Solid-State Circuits Conference. Digest of Technical Papers. ISSCC. First Edition (Cat. No.99CH36278), P76, DOI 10.1109/ISSCC.1999.759110
[5]   Transistor- and circuit-design optimization for low-power CMOS [J].
Chang, Mi-Chang ;
Chang, Chih-Sheng ;
Chao, Chih-Ping ;
Goto, Ken-Ichi ;
Ieong, Meikei ;
Lu, Lee-Chung ;
Diaz, Carlos H. .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :84-95
[6]   Evolution on SoC integration:: GSM baseband-radio in 0.13 μm CMOS extended by fully integrated power management unit [J].
Hammes, Markus ;
Kranz, Christian ;
Seippel, Dietolf ;
Kissing, Jens ;
Leyk, Andreas .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2008, 43 (01) :236-245
[7]   High-performance sub-0.08 μm CMOS with dual gate oxide and 9.7 ps inverter delay [J].
Hargrove, M ;
Crowder, S ;
Nowak, E ;
Logan, R ;
Han, LK ;
Ng, H ;
Ray, A ;
Sinitsky, D ;
Smeys, P ;
Guarin, F ;
Oberschmidt, J ;
Crabbé, E ;
Yee, D ;
Su, L .
INTERNATIONAL ELECTRON DEVICES MEETING 1998 - TECHNICAL DIGEST, 1998, :627-630
[8]   A Cu-Plate-Bonded System-in-Package (SiP) With Low Spreading Resistance of Topside Electrodes for Voltage Regulators [J].
Hashimoto, Takayuki ;
Uno, Tomoaki ;
Shiraishi, Masaki ;
Kawashima, Tetsuya ;
Akiyama, Noboru ;
Matsuura, Nobuyoshi ;
Akagi, Hirofumi .
IEEE TRANSACTIONS ON POWER ELECTRONICS, 2010, 25 (09) :2310-2319
[9]   High voltage tolerant linear regulator with fast digital control for biasing of integrated DC-DC converters [J].
Hazucha, Peter ;
Moon, Sung Tae ;
Schrom, Gerhard ;
Paillet, Fabrice ;
Gardner, Donald ;
Rajapandian, Saravanan ;
Karnik, Tanay .
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2007, 42 (01) :66-73
[10]   Low power and power management for CMOS - An EDA perspective [J].
Kawa, Jamil .
IEEE TRANSACTIONS ON ELECTRON DEVICES, 2008, 55 (01) :186-196