Hybrid NOrec: A Case Study in the Effectiveness of Best Effort Hardware Transactional Memory

被引：47

作者：

Dalessandro, Luke ^{[1
]}

Carouge, Francois ^{[2
]}

White, Sean ^{[2
]}

Lev, Yossi ^{[3
]}

Moir, Mark ^{[3
]}

Scott, Michael L. ^{[1
]}

Spear, Michael F. ^{[2
]}

机构：

[1] Univ Rochester, Rochester, NY 14627 USA

[2] Lehigh Univ, Bethlehem, PA 18015 USA

[3] Oracle Labs, Menlo Pk, CA USA

来源：

ACM SIGPLAN NOTICES | 2011年 / 46卷 / 03期

关键词：

Algorithms; Design; Transactional Memory;

D O I：

10.1145/1961296.1950373

中图分类号：

TP31 [计算机软件];

学科分类号：

081202 ; 0835 ;

摘要：

Transactional memory (TM) is a promising synchronization mechanism for the next generation of multicore processors. Best-effort Hardware Transactional Memory (HTM) designs, such as Sun's prototype Rock processor and AMD's proposed Advanced Synchronization Facility (ASF), can efficiently execute many transactions, but abort in some cases due to various limitations. Hybrid TM systems can use a compatible software TM (STM) in such cases. We introduce a family of hybrid TMs built using the recent NOrec STM algorithm that, unlike existing hybrid approaches, provide both low overhead on hardware transactions and concurrent execution of hardware and software transactions. We evaluate implementations for Rock and ASF, exploring how the differing HTM designs affect optimization choices. Our investigation yields valuable input for designers of future best-effort HTMs.

引用

页码：39 / 51

页数：13

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