Agile All-Digital RF Transceiver Implemented in FPGA

被引:19
作者
Cordeiro, R. F. [1 ]
Prata, Andre [1 ]
Oliveira, Arnaldo S. R. [1 ]
Vieira, Jose M. N. [1 ]
De Carvalho, N. B. [1 ]
机构
[1] Univ Aveiro, Dept Elect Telecomunicacoes & Informat, Inst Telecomunicacoes, P-3810193 Aveiro, Portugal
关键词
All-digital transceivers; delta-sigma modulation (DSM); pulsewidth modulation (PWM); software-defined radio (SDR); MODULATOR; TRANSMITTERS; QUANTIZATION; ARCHITECTURE; EFFICIENCY; SPECTRUM; ADC;
D O I
10.1109/TMTT.2017.2689739
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper presents a new all-digital transceiver architecture fully integrated into a single field-programmable gate array chip. Both the radio frequency (RF) receiver and the transmitter were entirely implemented using a digital datapath from the baseband up to the RF stage without the use of conventional analog-to-digital converter, digital-to-analog converter, or analog mixer. The transmitter chain uses delta-sigma modulation and digital upconversion to produce a two-level RF output signal. The receiver uses a high-speed comparator and pulsewidth modulation to convert the RF signal into a single-bit data stream, which is digitally filtered and then downconverted. Both the transmitter and the receiver are agile with flexible carrier frequency, bandwidth, and modulation capabilities. The transceiver error vector magnitude and the signal-to-noise ratio figures of merit were analyzed in a point-to-point transmission to evaluate the transmitter's performance. The results show the feasibility of this approach as a more flexible alternative to common radio architectures.
引用
收藏
页码:4229 / 4240
页数:12
相关论文
共 33 条
[1]   What Will 5G Be? [J].
Andrews, Jeffrey G. ;
Buzzi, Stefano ;
Choi, Wan ;
Hanly, Stephen V. ;
Lozano, Angel ;
Soong, Anthony C. K. ;
Zhang, Jianzhong Charlie .
IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 2014, 32 (06) :1065-1082
[2]  
[Anonymous], 2010, Handbook of Mathematical Functions
[3]  
[Anonymous], P IEEE COMP SEM INT
[4]  
[Anonymous], 2011, C RAN ROAD GREEN RAN
[5]   A 4th Order 3.6 GS/s RF ΣΔ ADC With a FoM of 1 pJ/bit [J].
Ashry, Ahmed ;
Aboushady, Hassan .
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2013, 60 (10) :2606-2617
[6]  
BILINSKIS I, 2007, DIGITAL ALIAS FREE S
[7]  
Bonghyuk Park, 2012, 2012 14th International Conference on Advanced Communication Technology (ICACT), P274
[8]  
Chen Jufang, 2011, Proceedings of the International Conference on Advanced Manufacturing Technology 2011 (ATDM 2011), P1, DOI 10.1049/cp.2011.1029
[9]   Gigasample Time-Interleaved Delta-Sigma Modulator for FPGA-based All-Digital Transmitters [J].
Cordeiro, Rui F. ;
Oliveira, Arnaldo S. R. ;
Vieira, Jose ;
Silva, Nelson V. .
2014 17TH EUROMICRO CONFERENCE ON DIGITAL SYSTEM DESIGN (DSD), 2014, :222-227
[10]  
Ebrahimi M. M., 2011, Progress In Electromagnetics Research B, V34, P263