High-Reliability Dynamic-Threshold Source-Side Injection for 2-Bit/Cell With MLC Operation of Wrapped Select-Gate SONOS in NOR-Type Flash Memory

被引：3

作者：

Wang, Kuan-Ti ^{[1
]}

Chao, Tien-Sheng ^{[1
]}

Wu, Woei-Cherng ^{[1
]}

Yang, Wen-Luh ^{[2
]}

Lee, Chien-Hsing ^{[3
]}

Hsieh, Tsung-Min ^{[3
]}

Liou, Jhyy-Cheng ^{[3
]}

Wang, Shen-De ^{[4
]}

Chen, Tzu-Ping ^{[4
]}

Chen, Chien-Hung ^{[4
]}

Lin, Chih-Hung ^{[4
]}

Chen, Hwi-Huang ^{[4
]}

机构：

[1] Natl Chiao Tung Univ, Dept Electrophys, Hsinchu 300, Taiwan

[2] Feng Chia Univ, Dept Elect Engn, Taichung 407, Taiwan

[3] Solid State Syst Co Ltd, Hsinchu 302, Taiwan

[4] United Microelect Corp, Special Technol Div, Hsinchu 300, Taiwan

来源：

IEEE TRANSACTIONS ON ELECTRON DEVICES | 2010年 / 57卷 / 09期

关键词：

Flash memory; multilevel states in a cell (MLC); NOR; silicon-oxide-nitride-oxide-silicon (SONOS);

D O I：

10.1109/TED.2010.2054530

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

For the first time, a high-performance (tau(PGM) = 200 ns/tau(ERS) = 5 ms) cell with superior reliability characteristics is demonstrated in a NOR-type architecture, using dynamic-threshold source-side injection (DTSSI) in a wrapped select-gate silicon-oxide-nitride-oxide-silicon memory device, with multilevel and 2-bit/cell operation. Using DTSSI enables easy extraction of the multilevel states with a tight V-TH distribution, a nearly negligible second-bit effect, superior endurance characteristics, and good data retention.

引用

页码：2335 / 2338

页数：4

共 13 条

[1] [Anonymous], VLSI TECHN SYST APPL
[2] [Anonymous], 2005, IEDM
[3] BAUER M, 1995, ISSCC DIG TECH PAP I, V38, P132, DOI 10.1109/ISSCC.1995.535462
[4] Modeling for the 2nd-bit effect of a nitride-based trapping storage flash EEPROM cell under two-bit operation
Chang, YW
Lu, TC
Pan, S
Lu, CY
[J]. IEEE ELECTRON DEVICE LETTERS, 2004, 25 (02) : 95 - 97
[5] NROM: A novel localized trapping, 2-bit nonvolatile memory cell
Eitan, B
Pavan, P
Bloom, I
Aloni, E
Frommer, A
Finzi, D
[J]. IEEE ELECTRON DEVICE LETTERS, 2000, 21 (11) : 543 - 545
[6] Root cause of charge loss in a nitride-based localized trapping memory cell
Furnemont, Arnaud
Rosmeulen, Maarten
van der Zanden, Koen
Van Houdt, Jan
De Meyer, Kristin
Maes, Herman
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2007, 54 (06) : 1351 - 1359
[7] Band engineered charge trap layer for highly reliable MLC flash memory
Huo, ZongLiang
Yang, JunKyu
Lim, SeungHyun
Baik, SeungJae
Lee, Juyul
Han, JeongHee
Yeo, In-Seok
Chung, U-In
Moon, Joo Tae
Ryu, Byung-Il
[J]. 2007 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS, 2007, : 138 - +
[8] Studies of the reverse read method and second-bit effect of 2-bit/cell nitride-trapping device by quasi-two-dimensional model
Lue, HT
Hsu, TH
Wu, MT
Hsieh, KY
Liu, R
Lu, CY
[J]. IEEE TRANSACTIONS ON ELECTRON DEVICES, 2006, 53 (01) : 119 - 125
[9] WANG KT, 2007, P IEEE MTDT, P51
[10] High-Speed Multilevel Wrapped-Select-Gate SONOS Memory Using a Novel Dynamic Threshold Source-Side-Injection (DTSSI) Programming Method
Wang, Kuan-Ti
Chao, Tien-Sheng
Wu, Woei-Cherng
Chiang, Tsung-Yu
Wu, Yi-Hong
Yang, Wen-Luh
Lee, Chien-Hsing
Hsieh, Tsung-Min
Liou, Jhyy-Cheng
Wang, Shen-De
Chen, Tzu-Ping
Chen, Chien-Hung
Lin, Chih-Hung
Chen, Hwi-Huang
[J]. IEEE ELECTRON DEVICE LETTERS, 2009, 30 (06) : 659 - 661

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