机构:
Natl Inst Technol NIT, Dept Elect & Commun, Tiruchirappalli, Tamil Nadu, IndiaNatl Inst Technol NIT, Dept Elect & Commun, Tiruchirappalli, Tamil Nadu, India
Abbas, C. Mohammed
[1
]
论文数: 引用数:
h-index:
机构:
Shukla, Abhishek
[1
]
Kavitha, R. K.
论文数: 0引用数: 0
h-index: 0
机构:
Natl Inst Technol NIT, Dept Elect & Commun, Tiruchirappalli, Tamil Nadu, IndiaNatl Inst Technol NIT, Dept Elect & Commun, Tiruchirappalli, Tamil Nadu, India
Kavitha, R. K.
[1
]
机构:
[1] Natl Inst Technol NIT, Dept Elect & Commun, Tiruchirappalli, Tamil Nadu, India
来源:
2015 INTERNATIONAL CONFERENCE ON VLSI SYSTEMS, ARCHITECTURE, TECHNOLOGY AND APPLICATIONS (VLSI-SATA)
|
2015年
关键词:
PTAT;
CTAT;
NTC (Negative Temperature coefficient);
PTC (Positive Temperature coefficient);
ADC (Analog to Digital Converter);
DAC (Digital to Analog Converter);
EQUALIZATION;
GENERATOR;
D O I:
暂无
中图分类号:
TP3 [计算技术、计算机技术];
学科分类号:
0812 ;
摘要:
This paper presents an optimized sub1V voltage reference circuit based on the Body-Bias technique [1], which operates at power supply 1V or less. This reference circuit generates a voltage equal to the threshold voltage (at absolute zero temperature) of the transistor used in the design. To achieve zero temperature variations, it compensates temperature variations of thermal voltage, which is Proportional to Absolute Temperature (PTAT) with that of transistor's threshold voltage, which is Compliment to Absolute Temperature (CTAT). Utilizing the concept of body-bias technique to put the transistors in deep sub-threshold region, successfully achieved ultra-low power design. Design Implementation in 0.18 mu m achieved a temperature coefficient of best 8PPM and an average Power consumption of the circuit is found to be 135nW.