An optimized reconfigurable architecture for hardware implementation of decimal arithmetic

Hardware and software implementations of decimal arithmetic have resurfaced in recen years to overcome the limitations of binary arithmetic. Traditionally, decimal arithmetic units have been designed as application-specific hardware modules. But there is an emerging trend towards the design and implementation of deciinal arithmetic operations on re configurable structures. This paper contributes to this trend by proposing a reconfigurabli architecture, namely DARA, for high performance implementation of decimal arithmetic operations. Some basic decimal arithmetic operations were implemented on DARA anc synthesized subsequently. The results show that DARA has a delay overhead of 26% an area overhead of 54% on average compared to an ASIC implementation of the same operations. At the same time, if those basic operations had been implemented on a moder commercial FPGA, DARA would have outperformed the commercial device in terms of de lay and area by a factor of almost 4 and 9, respectively. (C) 2017 Elsevier Ltd. All rights reserved