A new frame-recompression algorithm and its hardware design for MPEG-2 video decoders

被引:49
作者
Lee, TY [1 ]
机构
[1] Hynix Semicond Inc, Syst IC SBU, SP BU, BT Team, Seoul 135738, South Korea
关键词
frame recompression; hardware design; low latency compression; memory reduction; MPEG-2;
D O I
10.1109/TCSVT.2003.813425
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
An algorithm and its implementation to recompress video frame data, which is to be stored into external memory, are proposed, thereby enabling reduction of memory requirements and bandwidth. To support random access capability, frames are organized as 1 x 8-pixel arrays, which are then compressed into. 32-bit segments. The compression ratio is fixed at 50%. For both compression efficiency and low complexity, modified Hadamard transform and Golomb-Rice (GR) coding are utilized. Objective and subjective video quality assessments are performed. Efficient hardware designs including GR encoding/decoding and packing/unpacking are also proposed to reduce the total compression/decompression latency cycles. The proposed hardware designs are suitable for the integration with MPEG-2 decoders thanks to fast operation and simple interface logic.
引用
收藏
页码:529 / 534
页数:6
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