Effect of Wiring Density and Pillar Structure on Chip Packaging Interaction for Mixed-Signal Cu Low k Chips

Multilevel finite element analysis (FEA) was used to study the effects of wiring density and solder pillar structure on chip-package interaction (CPI) for advanced Cu/low k mixed-signal chips. The mixed signal chip has analog and digital wiring designs with different metal densities, incorporating extreme low-k (ELK), low-k (LK) and oxide dielectrics in 10 wiring layers. The results are compared with uniform signal chips with uniform metal density on each wiring layer. The first principal stress was found to increase by 1.5 to 3x in the mixed signal chip between the analog and the isolation channel of the ELK and LK layers due to the different wiring density. In addition, the energy release rate (ERR) was significantly increased to reach a critical ERR ratio higher than 1 to drive interfacial delamination, raising serious chip-package interaction (CPI) reliability concern for the mixed signal chip. The results were attributed to the Dundurs effect due to the material mismatch and the nonuniform metal density in the mixed signal chip. In the study of the pillar structure effect, intermetallic compound (IMC) growth was found to be important and can substantially increase the critical ERR ratio to degrade the CPI reliability of the mixed signal chip.