Low-power multirate architecture for IF digital frequency down converter

被引：14

作者：

Jou, SJ ^{[1
]}

Wu, SY ^{[1
]}

Wang, CK ^{[1
]}

机构：

[1] Natl Cent Univ, Dept Elect Engn, Chungli 32054, Taiwan

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-ANALOG AND DIGITAL SIGNAL PROCESSING | 1998年 / 45卷 / 11期

关键词：

frequency down converter; low power; multirate architecture;

D O I：

10.1109/82.735360

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, a novel low-power multirate architecture for an IF digital frequency downconversion process is presented. The architecture design is the combination of 4-IF oversampling technique and multistage interpolated finite impulse response (IFIR) filter design based on multirate algorithm. It can have very low power dissipation owing to its reduction in hardware complexity and operational frequency. The design example shows that it consumes only 24% power of direct implementation while occupying 26% less area.

引用

页码：1487 / 1494

页数：8

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