18 GHz low-power CMOS static frequency divider

被引：14

作者：

Gu, Z ^{[1
]}

Thiede, A ^{[1
]}

机构：

[1] Univ Gesamthsch Paderborn, D-33095 Paderborn, Germany

来源：

ELECTRONICS LETTERS | 2003年 / 39卷 / 20期

关键词：

D O I：

10.1049/el:20030932

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A pseudo-differential latch circuit is investigated. By removing the current source from the conventional source-coupled field-effect-transistor logic (SCFL) structure, the speed of the circuit can be improved. The pseudo-differential D-type flip-flop-based 2:1 static frequency divider. which can operate up to 18 GHz and consumes less than 4 mA from a 1.8 V supply. has been realised in 0.18 mum standard digital CMOS technology.

引用

页码：1433 / 1434

页数：2

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