Scalability of spin field programmable gate arrary: A reconfigurable architecture based on spin metal-oxide-semiconductor field effect transistor

被引：21

作者：

Tanamoto, Tetsufumi ^{[1
]}

Sugiyama, Hideyuki ^{[1
]}

Inokuchi, Tomoaki ^{[1
]}

Marukame, Takao ^{[1
]}

Ishikawa, Mizue ^{[1
]}

Ikegami, Kazutaka ^{[1
]}

Saito, Yoshiaki ^{[1
]}

机构：

[1] Toshiba Corp 1, Adv LSI Technol Lab, Corp Res & Dev Ctr, Saiwai Ku, Kawasaki, Kanagawa 2128582, Japan

来源：

JOURNAL OF APPLIED PHYSICS | 2011年 / 109卷 / 07期

关键词：

D O I：

10.1063/1.3537923

中图分类号：

O59 [应用物理学];

学科分类号：

摘要：

The scalability of a field programmable gate array (FPGA) using a spin metal-oxide-semiconductor field effect transistor (MOSFET) (spin FPGA) with a magnetocurrent (MC) ratio in the range of 100-1000% is discussed for the first time. The area and speed of million-gate spin FPGAs are numerically benchmarked with CMOS FPGA for 22, 32, and 45 nm technologies including a 20% transistor size variation. We show that the area is reduced and the speed is increased in spin FPGA due to the nonvolatile memory function of spin MOSFET. (C) 2011 American Institute of Physics. [doi:10.1063/1.3537923]

引用

页数：3

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