The design of compressed memory system for depth data in 3D rendering processors

被引：0

作者：

Park, Woo-Chan ^{[1
]}

Yoon, Duk-Ki ^{[1
]}

Kim, Dong-Seok ^{[1
]}

Kim, Hong-Sik ^{[2
]}

Park, Jin-Hong ^{[2
]}

Jeong, Woo-Nam ^{[2
]}

Han, Tack-Don ^{[2
]}

机构：

[1] Sejong Univ, Dept Comp Engn, Seoul 143747, South Korea

[2] Yonsei Univ, Dept Comp Sci, Seoul 120749, South Korea

来源：

IEICE ELECTRONICS EXPRESS | 2010年 / 7卷 / 21期

关键词：

graphics processor; memory system; compression;

D O I：

10.1587/elex.7.1622

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We propose an effective compressed memory system to address bandwidth problem of depth data for low-power 3D rendering processors. The proposed memory system performs on-the-fly compression for depth data to be stored into external memory. If the compression rate meets or exceeds a selected threshold value, then the compressed depth data are stored into internal SRAM; otherwise the original depth data are stored into external DRAM. Experimental simulation results show that the proposed memory system could reduces the external DRAM usage by about 82%.

引用

页码：1622 / 1628

页数：7