Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems

被引:10
|
作者
Bourge, Alban [1 ]
Muller, Olivier [1 ]
Rousseau, Frederic [1 ]
机构
[1] Univ Grenoble Alpes, TIMA Lab, F-38031 Grenoble, France
来源
2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM) | 2015年
关键词
FPGA; HLS; CAD; hardware context switch;
D O I
10.1109/FCCM.2015.8
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Modern FPGAs provide great computational power and flexibility but there is still room for improving their performances. For example multi-user approaches are particularly underdeveloped as they require specific mechanisms still to be automated. Sharing an FPGA resource between applications or users requires a context switch ability. The latter enables pausing and resuming applications at system demand. This paper presents a method that automatically selects a good execution point, called hardware checkpoint, to perform a context switch on an FPGA. The method relies on a static analysis of the finite state machine of a circuit to select the checkpoint states. The obtained selection ensures that the context switch mechanism respects a given latency and tries to minimize the mechanism costs. The method takes advantage of its integration in an open-source HLS tool and preliminary results highlight its efficiency.
引用
收藏
页码:155 / 158
页数:4
相关论文
共 50 条
  • [41] A Reconfigurable Hardware Platform for Power Converter Control Systems
    Villa, Paulo R. C.
    Bezerra, Eduardo A.
    Lettnin, Djones V.
    Mussa, Samir A.
    2015 IEEE INTERNATIONAL CONFERENCE ON INDUSTRIAL TECHNOLOGY (ICIT), 2015, : 1560 - 1563
  • [42] High-Level Programming of FPGA-Accelerated Systems with Parallel Patterns
    Birath, Bjorn
    Ernstsson, August
    Tinnerholm, John
    Kessler, Christoph
    INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING, 2024, 52 (04) : 253 - 273
  • [43] Fault Tolerance Properties of Systems Generated with the Use of High-Level Synthesis
    Lojda, Jakub
    Podivinsky, Jakub
    Kotasek, Zdenek
    PROCEEDINGS OF 2018 IEEE EAST-WEST DESIGN & TEST SYMPOSIUM (EWDTS 2018), 2018,
  • [44] Rapid Prototyping of Image Contrast Enhancement Hardware Accelerator on FPGAs Using High-Level Synthesis Tools
    Bilal, Muhammad
    Harasani, Wail Ismael
    Yang, Liang
    JORDAN JOURNAL OF ELECTRICAL ENGINEERING, 2023, 9 (03): : 322 - 337
  • [45] A hardware architecture for single and multiple ellipse detection using genetic algorithms and high-level synthesis tools
    Iniguez-Lomeli, Francisco J.
    Garcia-Capulin, Carlos H.
    Rostro-Gonzalez, Horacio
    MICROPROCESSORS AND MICROSYSTEMS, 2024, 111
  • [46] Light-weight color image conversion like pencil drawing for high-level synthesized hardware
    Honoka Tani
    Akira Yamawaki
    Artificial Life and Robotics, 2024, 29 : 29 - 36
  • [47] Implementation of heapsort in programmable logic with High-Level Synthesis
    Zabolotny, Wojciech M.
    PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2018, 2018, 10808
  • [48] Implementation of OMTF trigger algorithm with High-Level Synthesis
    Zabolotny, Wojciech M.
    PHOTONICS APPLICATIONS IN ASTRONOMY, COMMUNICATIONS, INDUSTRY, AND HIGH-ENERGY PHYSICS EXPERIMENTS 2019, 2019, 11176
  • [49] Challenges Designing for FPGAs Using High-Level Synthesis
    Faber, Clayton J.
    Harris, Steven D.
    Xiao, Zhili
    Chamberlain, Roger D.
    Cabrera, Anthony M.
    2022 IEEE HIGH PERFORMANCE EXTREME COMPUTING VIRTUAL CONFERENCE (HPEC), 2022,
  • [50] Light-weight color image conversion like pencil drawing for high-level synthesized hardware
    Tani, Honoka
    Yamawaki, Akira
    ARTIFICIAL LIFE AND ROBOTICS, 2024, 29 (01) : 29 - 36