Automatic High-Level Hardware Checkpoint Selection for Reconfigurable Systems

被引:10
|
作者
Bourge, Alban [1 ]
Muller, Olivier [1 ]
Rousseau, Frederic [1 ]
机构
[1] Univ Grenoble Alpes, TIMA Lab, F-38031 Grenoble, France
来源
2015 IEEE 23RD ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES (FCCM) | 2015年
关键词
FPGA; HLS; CAD; hardware context switch;
D O I
10.1109/FCCM.2015.8
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
Modern FPGAs provide great computational power and flexibility but there is still room for improving their performances. For example multi-user approaches are particularly underdeveloped as they require specific mechanisms still to be automated. Sharing an FPGA resource between applications or users requires a context switch ability. The latter enables pausing and resuming applications at system demand. This paper presents a method that automatically selects a good execution point, called hardware checkpoint, to perform a context switch on an FPGA. The method relies on a static analysis of the finite state machine of a circuit to select the checkpoint states. The obtained selection ensures that the context switch mechanism respects a given latency and tries to minimize the mechanism costs. The method takes advantage of its integration in an open-source HLS tool and preliminary results highlight its efficiency.
引用
收藏
页码:155 / 158
页数:4
相关论文
共 50 条
  • [1] Malacoda: Towards High-Level Compilation of Network Security Applications on Reconfigurable Hardware
    Muehlbach, Sascha
    Koch, Andreas
    PROCEEDINGS OF THE EIGHTH ACM/IEEE SYMPOSIUM ON ARCHITECTURES FOR NETWORKING AND COMMUNICATIONS SYSTEMS (ANCS'12), 2012, : 247 - 257
  • [2] A Reconfigurable Platform and Programming Tools for High-Level Network Applications Demonstrated as a Hardware Honeypot
    Muehlbach, Sascha
    Koch, Andreas
    IEEE JOURNAL ON SELECTED AREAS IN COMMUNICATIONS, 2014, 32 (10) : 1919 - 1932
  • [3] Distributed control for reconfigurable FPGA systems: a high-level design approach
    Trabelsi, Chiraz
    Meftali, Samy
    Dekeyser, Jean-Luc
    2012 7TH INTERNATIONAL WORKSHOP ON RECONFIGURABLE AND COMMUNICATION-CENTRIC SYSTEMS-ON-CHIP (RECOSOC), 2012,
  • [4] High-Level Synthesis Toolchain “Theseus” for Multichip Reconfigurable Computer Systems
    Dordopulo A.I.
    Levin I.I.
    Gudkov V.A.
    Gulenok A.A.
    Supercomputing Frontiers and Innovations, 2023, 10 (02) : 18 - 31
  • [5] The FPOA, a Medium-grained Reconfigurable Architecture for High-level Synthesis
    Gorski, Joson
    Hanna, Darrin
    ACM TRANSACTIONS ON RECONFIGURABLE TECHNOLOGY AND SYSTEMS, 2019, 12 (04)
  • [6] High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
    Endri Bezati
    Richard Thavot
    Ghislain Roquier
    Marco Mattavelli
    Journal of Real-Time Image Processing, 2014, 9 : 251 - 262
  • [7] High-level dataflow design of signal processing systems for reconfigurable and multicore heterogeneous platforms
    Bezati, Endri
    Thavot, Richard
    Roquier, Ghislain
    Mattavelli, Marco
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2014, 9 (01) : 251 - 262
  • [8] Reconfigurable 3D Sound Processor and Its Automatic Design Environment Using High-Level Synthesis
    Ohira, Saya
    Tsuchiya, Naoki
    Matsumura, Tetsuya
    IEICE TRANSACTIONS ON FUNDAMENTALS OF ELECTRONICS COMMUNICATIONS AND COMPUTER SCIENCES, 2019, E102A (12) : 1804 - 1812
  • [9] An Automated High-level Design Framework for Partially Reconfigurable FPGAs
    Kumar, Rohit
    Gordon-Ross, Ann
    2015 IEEE 29TH INTERNATIONAL PARALLEL AND DISTRIBUTED PROCESSING SYMPOSIUM WORKSHOPS, 2015, : 170 - 175
  • [10] Hardware Implementation of the SUMIS Detector using High-Level Synthesis
    Haselmayr, Werner
    Moestl, Georg
    Seeber, Stefan
    Springer, Andreas
    2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 2972 - 2975