Synthesis of Fast Finite State Machines on Programmable Logic Integrated Circuits by Splitting Internal States

A method for the synthesis of fast finite state machines on programmable logic integrated circuits such as field-programmable gate arrays is presented. The method is based on the operation of splitting internal states, which makes it possible to reduce the ranks of transition functions and reduce the number of levels of functional generators when implementing transition functions. Estimates are given for the number of levels of functional generators in the implementation of the transition functions of a finite state machine in the case of sequential and parallel decomposition. An algorithm for splitting internal states for the synthesis of fast finite state machines is described. The results of experimental studies show that the proposed method allows increasing the speed of finite state machines by factors of 1.08 to 1.19 on average, and by factors of 1.52 to 1.73 at most. The presented method is also compared with the JEDI and NOVA university programs.