Synthesis of Fast Finite State Machines on Programmable Logic Integrated Circuits by Splitting Internal States

被引：6

作者：

Solov'ev, V. V. ^{[1
]}

机构：

[1] Bialystok Tech Univ, Bialystok, Poland

来源：

JOURNAL OF COMPUTER AND SYSTEMS SCIENCES INTERNATIONAL | 2022年 / 61卷 / 03期

关键词：

Field programmable gate arrays (FPGA) - Integrated circuits - Logic gates - Logic Synthesis - Programmable logic controllers - Timing circuits;

D O I：

10.1134/S1064230722030133

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

A method for the synthesis of fast finite state machines on programmable logic integrated circuits such as field-programmable gate arrays is presented. The method is based on the operation of splitting internal states, which makes it possible to reduce the ranks of transition functions and reduce the number of levels of functional generators when implementing transition functions. Estimates are given for the number of levels of functional generators in the implementation of the transition functions of a finite state machine in the case of sequential and parallel decomposition. An algorithm for splitting internal states for the synthesis of fast finite state machines is described. The results of experimental studies show that the proposed method allows increasing the speed of finite state machines by factors of 1.08 to 1.19 on average, and by factors of 1.52 to 1.73 at most. The presented method is also compared with the JEDI and NOVA university programs.

引用

页码：360 / 371

页数：12

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