Numerical simulation and optimization for 900V 4H-SiC DiMOSFET fabrication

被引：1
|
作者：
Kim, SC
Bahng, W
Kim, NK
Kim, ED
Ayalew, T
Grasser, T
Selberherr, S
机构：
[1] Korea Electrotechnol Res Inst, Power Semicond Res Grp, Chang Won 641120, Gyungnam, South Korea
[2] TU Vienna, Christian Doppler Lab TCAD Microelect Inst Microe, A-1040 Vienna, Austria
[3] TU Vienna, Inst Microelect, A-1040 Vienna, Austria
来源：
SILICON CARBIDE AND RELATED MATERIALS 2004 | 2005年 / 483卷
关键词：
DiMOSFET; edge termination; silicon carbide; MINIMOS-NT;
D O I：
10.4028/www.scientific.net/MSF.483-485.793
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
We report the simulation results of 25μ m half cell pitch vertical type 4H-SiC DiMOSFET using the general-purpose device simulator MINIMOS-NT. The best trade-off between breakdown voltage and on-resistance in terms of BFOM is around 19MW/cm(2) with a p-well spacing 5 μ m. The specific on -resistance, R-ON, sp, simulated with V-GS=10V and V-DS= 1 V at room temperature, is around 22.76mΩ cm(2). An 900V breakdown voltage is simulated with ion-implanted edge termination.
引用
收藏
页码：793 / 796
页数：4
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