Impact of process parameters on circuit performance for the 32 nm technology node

被引：3
作者：
Farcy, A.
Gallitre, M.
Arnal, V.
Sellier, M.
Guibe, L.
Blampey, B.
Bermond, C.
Flechet, B.
Torres, J.
机构：
[1] STMicroelect, F-38926 Crolles, France
[2] Univ Savoie, LAHC, Le Bourget Du Lac, France
[3] NXP Semicond, F-38926 Crolles, France
来源：
MICROELECTRONIC ENGINEERING | 2007年 / 84卷 / 11期
关键词：
interconnects; propagation; performance; delay; circuit optimization; 32 nm node;
D O I：
10.1016/j.mee.2007.05.015
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
As IC dimensions scale down to the 32 nm technology node, interconnect is more than ever the most limiting factor affecting overall circuit performance. The influence of all involved process parameters were studied as a function of target application through electromagnetic and time domain simulations, and compared to the impact of driver characteristics. As a result, an optimization of the BEOL stack was performed to propose process and material recommendations meeting electrical specifications for most circuit applications. (c) 2007 Elsevier B.V. All rights reserved.
引用
收藏
页码：2738 / 2743
页数：6
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