Testing TAPed cores and wrapped cores with the same test access mechanism

被引：10
作者：
Benabdenbi, M [1 ]
Maroufi, W [1 ]
Marzouki, M [1 ]
机构：
[1] LIP6 Lab, F-75252 Paris 05, France
来源：
DESIGN, AUTOMATION AND TEST IN EUROPE, CONFERENCE AND EXHIBITION 2001, PROCEEDINGS | 2001年
关键词：
D O I：
10.1109/DATE.2001.915016
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes a way of resting both wrapped cores and TAPed cores within a System On a Chip (SoC) with the same Test Access Mechanism (TAM). The TAM's architecture, which is dynamically reconfigurable, scalable and flexible, is named GAS-BUS and have a central controller: All the cores can be tested this way in the same session through a modified Boundary Scan Test Access Port.
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收藏
页码：150 / 155
页数：6
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