Microeconomics of overlay control at the 65nm technology node

ITRS working groups have identified overlay control as a technology roadblock with no known solutions at the 65nm node and beyond. The most serious problems are total measurement uncertainty, CMP process robustness, and device correlation. A systematic root-cause analysis of pattern placement error (PPE) at Motorola's Dan Noble Center has determined that current box-in-box overlay targets cause deficiencies in all three categories. A Proposed solution utilizes advanced imaging targets that are grating-based and can be segmented with features that are similar to those in the device. In the case of poly-to-STI overlay using 193nm lithography tools, these targets show a 40% decrease in total measurement uncertainty.