ROM based logic (RBL) design: High-performance and low-power adders

被引：2

作者：

Paul, Bipul C. ^{[1
]}

Fujita, Shinobu ^{[1
]}

Okajima, Masaki ^{[1
]}

机构：

[1] Toshiba Amer Res Inc, San Jose, CA 95131 USA

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

10.1109/ISCAS.2008.4541538

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32bit adder) delay reduction over their conventional designs at 90nm technology with as low as 9% (CSA) active power increase.

引用

页码：796 / 799

页数：4

共 50 条

[31] High-performance low-power left-to-right array multiplier design
Huang, ZJ
Ercegovac, MSD
IEEE TRANSACTIONS ON COMPUTERS, 2005, 54 (03) : 272 - 283
[32] Development of architecture and software technologies in high-performance low-power SoC design
Hsueh, CW
Chen, TF
Chang, RG
Lo, SW
11TH IEEE INTERNATIONAL CONFERENCE ON EMBEDDED AND REAL-TIME COMPUTING SYSTEMS AND APPLICATIONS, PROCEEDINGS, 2005, : 475 - 480
[33] LPRAM: A novel methodology for low-power high-performance RAM design with testability
Bhattacharjee, S
Pradhan, DK
IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2004, 23 (05) : 637 - 651
[34] Carbon nanotube electronics: Design of high-performance and low-power digital circuits
Raychowdhury, Arijit
Roy, Kaushik
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2007, 54 (11) : 2391 - 2401
[35] Novel high-density low-power high-performance double-gate logic techniques
Chiang, MH
Kim, K
Tretz, C
Chuang, CT
2004 IEEE INTERNATIONAL SOI CONFERENCE, PROCEEDINGS, 2004, : 122 - 123
[36] Design of high-speed low-power parallel-prefix VLSI adders
Dimitrakopoulos, G
Kolovos, P
Kalogerakis, P
Nikolos, D
INTEGRATED CIRCUIT AND SYSTEM DESIGN: POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION, 2004, 3254 : 248 - 257
[37] A HIGH-PERFORMANCE LOW-POWER CMOS CHANNEL FILTER
BLACK, WC
ALLSTOT, DJ
REED, RA
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 1980, 15 (06) : 929 - 938
[38] A Low-Power, High-Performance Speech Recognition Accelerator
Yazdani, Reza
Arnau, Jose-Maria
Gonzalez, Antonio
IEEE TRANSACTIONS ON COMPUTERS, 2019, 68 (12) : 1817 - 1831
[39] Low-power high-performance FinFET sequential circuits
Tawfik, Shenf A.
Kursuri, Volkan
20TH ANNIVERSARY IEEE INTERNATIONAL SOC CONFERENCE, PROCEEDINGS, 2007, : 145 - 148
[40] A low-power high-performance embedded SRAM macrocell
Fahim, AM
Khellah, M
Elmasry, MI
PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 13 - 18

← 1 2 3 4 5 →