ROM based logic (RBL) design: High-performance and low-power adders

被引：2

作者：

Paul, Bipul C. ^{[1
]}

Fujita, Shinobu ^{[1
]}

Okajima, Masaki ^{[1
]}

机构：

[1] Toshiba Amer Res Inc, San Jose, CA 95131 USA

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

10.1109/ISCAS.2008.4541538

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32bit adder) delay reduction over their conventional designs at 90nm technology with as low as 9% (CSA) active power increase.

引用

页码：796 / 799

页数：4

共 50 条

[21] ARM6 - PROCESSOR DESIGN FOR HIGH-PERFORMANCE AT LOW-POWER
MULLER, M
VLSI 93, 1994, 42 : 181 - 189
[22] Design, optimization of low-power high-performance DSP building blocks
Gemmeke, T
Gansen, M
Stockmans, HJ
Noll, TG
IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (07) : 1131 - 1139
[23] Design and Implementation of Imprecise Adders for Low-Power Applications
Manga, N. Alivelu
Nikhila, Varala Pasula
ADVANCES IN SIGNAL PROCESSING AND COMMUNICATION ENGINEERING, ICASPACE 2021, 2022, 929 : 205 - 213
[24] Selectively clocked skewed logic (SCSL): A robust low-power logic style for high-performance applications
Sirisantana, N
Cao, AQ
Davidson, S
Koh, CK
Roy, K
ISLPED'01: PROCEEDINGS OF THE 2001 INTERNATIONAL SYMPOSIUM ON LOWPOWER ELECTRONICS AND DESIGN, 2001, : 267 - 270
[25] High-performance low-power FFT cores
Han, Wei
Erdogan, Ahmet T.
Arslan, Tughrul
Hasan, Mohd.
ETRI JOURNAL, 2008, 30 (03) : 451 - 460
[26] Design and Analysis of Low-Power and High Speed Approximate Adders Using CNFETs
Bhargav, Avireni
Huynh, Phat
SENSORS, 2021, 21 (24)
[27] Advanced CMOS transistors in the nanotechnology era for high-performance, low-power logic applications
Chau, R
Doczy, M
Doyle, B
Datta, S
Dewey, G
Kavalieros, J
Jin, B
Metz, M
Majumdar, A
Radosavljevic, M
2004: 7TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUITS TECHNOLOGY, VOLS 1- 3, PROCEEDINGS, 2004, : 26 - 30
[28] Low-Power and High-Performance Design for Cryptosystem Using Power Aware and Pipeline Techniques
Minh-Tung Dam
Van-Cuong Nguyen
Trong-Tuan Nguyen
Thang-Dong Tran Le
2014 INTERNATIONAL CONFERENCE ON ADVANCED TECHNOLOGIES FOR COMMUNICATIONS (ATC), 2014, : 36 - 41
[29] An Analysis of Parallel Prefix Adders Regarding the Design of Low-Power Data Oriented Adders
Brzozowski, Ireneusz
2018 INTERNATIONAL CONFERENCE ON SIGNALS AND ELECTRONIC SYSTEMS (ICSES 2018), 2018, : 7 - 12
[30] A novel high-performance and low-power mesh-based NoC
Sabbaghi-Nadooshan, Reza
Modarressi, Mehdi
Sarbazi-Azad, Hamid
2008 IEEE INTERNATIONAL SYMPOSIUM ON PARALLEL & DISTRIBUTED PROCESSING, VOLS 1-8, 2008, : 3225 - +

← 1 2 3 4 5 →