ROM based logic (RBL) design: High-performance and low-power adders

被引：2

作者：

Paul, Bipul C. ^{[1
]}

Fujita, Shinobu ^{[1
]}

Okajima, Masaki ^{[1
]}

机构：

[1] Toshiba Amer Res Inc, San Jose, CA 95131 USA

来源：

PROCEEDINGS OF 2008 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-10 | 2008年

关键词：

D O I：

10.1109/ISCAS.2008.4541538

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

We present a ROM based logic design technique using reduced ROM size by eliminating identical rows and columns along with fast and low power single transistor cells. It substantially reduces the critical path length and thereby, improves the performance yet achieves low-power dissipation due to reduced number of switching. We present the ROM based design of a carry select adder (CSA) and two parallel prefix adders, which achieve more than 30% (in 32bit adder) delay reduction over their conventional designs at 90nm technology with as low as 9% (CSA) active power increase.

引用

页码：796 / 799

页数：4

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