Analysis, estimation and reduction of simultaneous switching noise

被引：1
作者：
Abderrahman, A
Savaria, Y
Kaminska, B
机构：
来源：
CANADIAN JOURNAL OF ELECTRICAL AND COMPUTER ENGINEERING-REVUE CANADIENNE DE GENIE ELECTRIQUE ET INFORMATIQUE | 1996年 / 21卷 / 04期
关键词：
D O I：
10.1109/CJECE.1996.7101991
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The performance of digital and mixed circuits is affected and limited by the simultaneous switching power and ground noise. This kind of noise is related to interconnections and packaging. The latter two factors play a major role in high-speed-circuit design and may become a dominant factor limiting the performance of future ULSI components. As a result, it is imperative to understand and to master the problems and subtleties arising from interconnections and packaging. Among these problems, that of simultaneous switching noise is taking on more and more importance as circuits become faster and their I/O pin count increases. This paper reviews the state of current research regarding how to analyze, estimate and reduce simultaneous switching noise.
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收藏
页码：133 / 143
页数：11
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