Mixed-signal test automation: are we there yet?

被引:2
作者
Leger, Gildas [1 ]
Barragan, Manuel J. [2 ,3 ]
机构
[1] Univ Seville, CSIC, Inst Microlect Sevilla, Av Amer Vespucio S-N, Seville 41092, Spain
[2] Univ Grenoble Alpes, CNRS, Grenoble INP, TIMA, F-38000 Grenoble, France
[3] Univ Grenoble Alpes, Inst Engn, Grenoble, France
来源
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS) | 2018年
关键词
ANALOG; OPTIMIZATION;
D O I
10.1109/ISCAS.2018.8351734
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Testing analog, mixed-signal and RF (AMS-RF) circuits represents a significant cost component for testing complex SoCs. Moreover, AMS-RF test generation and validation are still largely handcrafted tasks that rely on expert design knowledge for each particular Device Under Test (DUT). Mixed-signal test automation has been sought by the test community for the last decades, trying to mimic the success of digital test approaches. Indeed, in the digital domain, test is vastly automated and standard techniques are already available (ATPGs, BIST, scan registers, etc.). In the last decade, a methodology based on leveraging the power of machine learning algorithms has been proposed for AMS-RF circuits that opens the door to a higher level of automation. In this paper we review recent results in this line and try to put together what could be such a complete methodology and what remains to be done.
引用
收藏
页数:5
相关论文
共 52 条
  • [1] [Anonymous], 2017, INT MIX SIGN TEST WO
  • [2] [Anonymous], 2017, 35 IEEE VLSI TEST S
  • [3] [Anonymous], 2011, INT TEST CONF P
  • [4] Testing analog and mixed-signal integrated circuits using oscillation-test method
    Arabi, K
    Kaminska, B
    [J]. IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 1997, 16 (07) : 745 - 753
  • [5] Ayari A.H., 2012, TEST C ITC 2012 IEEE, P1
  • [6] Ayari H, 2012, IEEE VLSI TEST SYMP, P19, DOI 10.1109/VTS.2012.6231074
  • [7] Barr M.A., 2016, Integrated Structural and Geomorphic Evolution of Displaced Fluvial Channels Along the Mojave San Andreas and Their Implications for Measurements of Slip Rate By Table of Contents!, P1
  • [8] Barragan MJ, 2013, PROC EUR TEST SYMP
  • [9] A Fully-Digital BIST Wrapper Based on Ternary Test Stimuli for the Dynamic Test of a 40 nm CMOS 18-bit Stereo Audio ΔΣ ADC
    Barragan, Manuel J.
    Alhakim, Rshdee
    Stratigopoulos, Haralampos-G.
    Dubois, Matthieu
    Mir, Salvador
    Le Gall, Herve
    Bhargava, Neha
    Bal, Ankur
    [J]. IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS I-REGULAR PAPERS, 2016, 63 (11) : 1876 - 1888
  • [10] A Procedure for Alternate Test Feature Design and Selection
    Barragan, Manuel J.
    Leger, Gildas
    [J]. IEEE DESIGN & TEST, 2015, 32 (01) : 18 - 25