III-V nMOSFETs - Some issues associated with roadmap worthiness (invited)

被引：9

作者：

Thayne, Iain ^{[1
]}

Bentley, Steven ^{[1
]}

Holland, Martin ^{[1
]}

Jansen, Wout ^{[1
]}

Li, Xu ^{[1
]}

Macintyre, Douglas ^{[1
]}

Thoms, Stephen ^{[1
]}

Shin, Byungha ^{[2
]}

Ahn, Jaesoo ^{[2
]}

McIntyre, Paul ^{[2
]}

机构：

[1] Univ Glasgow, Nanoelect Res Ctr, Glasgow, Lanark, Scotland

[2] Stanford Univ, Dept Mat Sci & Engn, Stanford, CA 94305 USA

来源：

MICROELECTRONIC ENGINEERING | 2011年 / 88卷 / 07期

基金：

英国工程与自然科学研究理事会;

关键词：

III-V MOSFETs;

D O I：

10.1016/j.mee.2011.03.100

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The high electron mobility of compound semiconductor materials, arising from the combination of low effective mass and materials dependent intervalley scattering mechanisms, can result in high velocity and low backscatter electrons being injected at the source side of a III-V nMOSFET. In combination, these factors have the potential to meet the highly challenging performance metrics of the International Technology Roadmap for Semiconductors (ITRS) [1] beyond the 15 nm technology generation, in particular the need to reduce supply voltages towards 0.5 V. This paper highlights some challenges over and above those of developing a high quality dielectric/III-V semiconductor interface, specifically in the areas of scaled source/drain contact formation and channel materials and device architectures which have to be addressed if III-V MOSFETs are to be a credible solution to enable continued scaling of the ITRS beyond 2018. (c) 2011 Elsevier B.V. All rights reserved.

引用

页码：1070 / 1075

页数：6

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