Dynamic instruction scheduling in a trace-based multi-threaded architecture

被引：0

作者：

Rounce, Peter A. ^{[1
]}

De Souza, Alberto F. ^{[2
]}

机构：

[1] UCL, Dept Comp Sci, London WC1E 6BT, England

[2] Univ Fed Espirito Santo, Dept Informat, BR-29075910 Vitoria, ES, Brazil

来源：

INTERNATIONAL JOURNAL OF PARALLEL PROGRAMMING | 2008年 / 36卷 / 02期

关键词：

simultaneous multi-threading; dynamic instruction scheduling; wide issue architectures; VLIW;

D O I：

10.1007/s10766-007-0062-1

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

Simulation results are presented using the hardware-implemented, trace-based dynamic instruction scheduler of our single process DTSVLIW architecture to schedule instructions from several processes into multiple streams of VLIW instructions for execution by a wide-issue, simultaneous multi-threading (SMT) execution engine. The scheduling process involves single instruction execution of each process, dynamically scheduling executed instructions into blocks of VLIW instructions cached for subsequent SMT execution: SMT provides a mechanism to reduce the impact of horizontal and vertical waste, and variable memory latencies, seen in the DTSVLIW. Preliminary experiments explore this extended model. Results achieve PE utilization of up to 87% on a 4-thread, 1-scalar, 8 PE design, with speed-ups of up to 6.3 that of a single processor. Noticeably it only needs a single scalar process to be scheduled at any time, with main memory fetches being 1-4% that of a single processor.

引用

页码：184 / 205

页数：22

共 19 条

[1] Dynamically scheduling VLIW instructions [J].