Performance and Comparative Analysis of Heterojunction Structure Based GAA-NWTFET for Low Power Applications

In this paper, a gate-all-around nanowire TFET structure is developed, making it a heterojunction structure with silicon germanium (SiGe_GAA_NWTFET) as source material and employing silicon material in both channel and drain regions. The proposed design is compared to a conventional silicon gate-all-around nanowire TFET (Si_GAA_NWTFET). The DC performance analysis of both devices using 3D Silvaco TCAD tool is examined. The proposed device shows a steeper characteristic and is created with the goal of maintaining a high I-ON/I-OFF ratio as well as reducing the leakage current. The proposed idea has produced fairly good outcomes, with the OFF current (I-OFF) being lowered to the order of 10(-16) A/mu m and has attained a lowest point sub-threshold slope of 34.92 mV/decade. An enhanced I-ON/I-OFF ratio on the order of 10(10) has been obtained for a channel length of 20 nm. The device's applicability for analog circuits is also validated by simulated RF analysis findings, which show that it has a high transconductance value. Since the device has a low value of I-OFF, it consumes power in the range of mu W, making it suitable for low-power applications.