Architecture and Performance Analysis of a DSP Sub-system For Multi-Channel Voice over Network (VoN) Gateways

被引：0

作者：

Rayala, Jitendra ^{[1
]}

Vemireddy, Krishna ^{[1
]}

机构：

[1] VeriSilicon Inc, Santa Clara, CA 95054 USA

来源：

2010 INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATIONS (SPCOM) | 2010年

关键词：

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A detailed system design methodology for architecting area optimized DSP sub-system for multi-channel voice gateways is presented. An architecture for a specific subsystem including memory organization and I/O bandwidth requirements is described. System level performance and characterization details of this sub-system in a 65nm generic process are provided. It is shown that a substantial reduction of 75% in sub-system memory area is achieved with only a small increase of 17% in peak processing load.

引用

页数：5