Design and implementation of an FPGA-based motion command generation chip

This study is aimed at developing a motion control command generation chip that can be used to perform acceleration/deceleration motion planning for general point-to-point motion applications. Instead of using the complex polynomial type method, the digital convolution method is adopted to implement trapezoidal and S-curve motion planning. In addition, the Digital Difference Analyzer (DDA) technique is employed to generate the output pulse. Moreover, in order to deal with the error in the number of output pulses when applied to point-to-point motions, a real-time output pulse compensation algorithm is developed to make sure that no output pulse error will occur. This study adopts a programmable hardware structure, in which both the Acc/Dec motion planning and DDA are implemented in an FPGA chip using VHDL for fast hardware verification.